Nonvolatile memory device and method of programming the same

ABSTRACT

In a method of programming a three-dimensional nonvolatile memory device, a program loop is executed at least one time, wherein the program loop includes a programming step for programming selected memory cells among the memory cells and a verifying step for verifying whether the selected memory cells are program-passed or not. In the programming the selected memory cells, a level of a voltage being applied to a common source line connected to the strings in common may be changed. Thus, in a program operation, power consumption which is needed to charge-discharge the common source line can be decreased while increasing boosting efficiency.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a Continuation of U.S. application Ser. No. 15/229,158, filedAug. 5, 2016, which is a Continuation of U.S. application Ser. No.14/527,461, filed Oct. 29, 2014, which issued a U.S. Pat. No. 9,424,931on Aug. 23, 2016, and which makes a claim of priority under 35 U.S.C.§119 to Korean Patent Application No. 10-2014-0012167, filed on Feb. 3,2014, the entire contents of which are hereby incorporated by reference.

BACKGROUND

The present inventive concept herein relates to semiconductor memorydevices, and more particularly, to methods of programming a nonvolatilesemiconductor memory device.

Semiconductor memory devices may be classified as either volatile memorydevices or nonvolatile memory devices. Volatile memory devices aregenerally characterized by the loss of stored data when a power supplyis interrupted. Examples of volatile memory devices include dynamicrandom access memory (DRAM) devices and static random access memory(SRAM) devices. Nonvolatile memory devices are generally characterizedby the retention of stored data even when a power supply is interrupted.Examples of nonvolatile memory devices include programmable read onlymemory (PROM) devices, erasable PROM (EPROM) devices, electrically EPROM(EEPROM) devices, flash memory devices, ferroelectric random accessmemory (FRAM) devices, magnetic random access memory (MRAM) devices,phase change random access memory (PRAM) devices, and resistive randomaccess memory (RRAM) devices.

Among nonvolatile memory devices, flash memory exhibits advantages ofhigh programming speed, low power consumption and high capacity datastorage. Thus, data storage devices including flash memory has beenwidely utilized.

A floating gate type flash memory stores bit information by implantingcharges into a floating gate formed of polysilicon. Separately, eachmemory cell of flash memory can store data as a single level cell (SLC)in which 1 bit (states 1, 0) is recorded in one memory cell, and a multilevel cell (MLC) in which at least 2 bits (e.g., states 11, 01, 00, 10)are recorded in one memory cell.

In a program operation of a flash memory, to increase boostingefficiency, a technology of increasing a voltage level of a commonsource line to a specific level may be applied. However, to achievethis, since a voltage level of the common source line has to be chargedand discharged to the same level at every program loop, powerconsumption may increase.

SUMMARY

Embodiments of the inventive concept provide a method of programming anonvolatile memory device including a plurality of memory cells disposedat a place where a plurality of cell strings crosses a plurality of wordlines. The method may include executing a program loop at least onetime, wherein the program loop comprises a programming step forprogramming selected memory cells among the plurality of memory cellsand a verifying step for verifying whether the selected memory cells areprogram-passed or not. In the programming step, all the program loopsare divided into a plurality of periods referring to a ratio of memorycells being inhibited to all the memory cells and a level of a voltagebeing applied to a common source line varies according to the dividedperiod unit.

Embodiments of the inventive concept also provide a nonvolatile memorydevice. The nonvolatile memory device may include a memory cell arraycomprising a plurality of memory cells vertically stacked on thesubstrate while being disposed at where a plurality of strings and aplurality of word lines being formed in a direction perpendicular to asubstrate cross one another; a row select circuit configured to deriveselected word lines among the plurality of word lines; a page bufferconnected to bit lines connected to the plurality of strings; and avoltage generator configured to supply a voltage to a common source lineconnected to the plurality of strings in common. The voltage beingapplied to the common source line varies depending on a ratio of memorycells being inhibited to all the memory cells.

Embodiments of the inventive concept also provide a method ofprogramming a nonvolatile memory device including a plurality of memorycells disposed at where a plurality of cell strings perpendicular to asubstrate crosses a plurality of word lines. The method may includeprogramming selected memory cells among the plurality of memory cells;verifying whether the selected memory cells are program-passed or not;and repeating the programming and the verifying at least one time. Andall program loops including the programming and the verifying aredivided into a plurality of periods referring to a ratio of memory cellsbeing inhibited to all the memory cells, and a level of a voltage beingapplied to a common source line varies according to the divided periodunit.

BRIEF DESCRIPTION OF THE FIGURES

Preferred embodiments of the inventive concept will be described belowin more detail with reference to the accompanying drawings. Theembodiments of the inventive concept may, however, be embodied indifferent forms and should not be constructed as limited to theembodiments set forth herein. Rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the inventive concept to those skilled in the art.Like numbers refer to like elements throughout.

FIG. 1 is a block diagram illustrating a data storage device inaccordance with exemplary embodiments of the inventive concept.

FIG. 2 is a block diagram illustrating an example of a flash memoryillustrated in FIG. 1.

FIG. 3 is a perspective view illustrating an example of athree-dimensional structure of a memory block illustrated in FIG. 2.

FIG. 4 is a top plan view illustrating A and B cross sections of amemory block illustrated in FIG. 3.

FIG. 5 is an equivalent circuit diagram of the memory block illustratedin FIG. 3.

FIG. 6A is a drawing illustrating a voltage being applied to a word linein a program operation in accordance with exemplary embodiments of theinventive concept.

FIG. 6B is a drawing illustrating a voltage being applied to a commonsource line in a program operation in accordance with exemplaryembodiments of the inventive concept.

FIG. 7A is a drawing illustrating a voltage being applied to a word linewhen a program operation is performed on a multi level cell.

FIG. 7B is a drawing illustrating a voltage being applied to a commonsource line in a program operation in accordance with exemplaryembodiments of the inventive concept.

FIGS. 8A, 8B and 8C are drawings illustrating examples of a voltagelevel applied to a common source line in one loop when a programoperation is performed.

FIG. 9 is a drawing illustrating a common source line driver inaccordance with exemplary embodiments of the inventive concept.

FIG. 10 is a block diagram illustrating an example that a data storagedevice in accordance with exemplary embodiments of the inventive conceptis applied to a memory card.

FIG. 11 is a block diagram illustrating an example that a data storagedevice in accordance with exemplary embodiments of the inventive conceptis applied to a solid state drive.

FIG. 12 is a block diagram illustrating an example of a constitution ofa SSD controller illustrated in FIG. 11.

FIG. 13 is a block diagram illustrating an example in which a datastorage device in accordance with exemplary embodiments of the inventiveconcept is embodied by an electronic device.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Embodiments of inventive concepts will be described more fullyhereinafter with reference to the accompanying drawings, in whichembodiments of the inventive concept are shown. This inventive conceptmay, however, be embodied in many different forms and should not beconstrued as limited to the embodiments set forth herein. Rather, theseembodiments are provided so that this disclosure will be thorough andcomplete, and will fully convey the scope of the inventive concept tothose skilled in the art. In the drawings, the size and relative sizesof layers and regions may be exaggerated for clarity. Like numbers referto like elements throughout.

FIG. 1 is a block diagram illustrating a data storage device inaccordance with exemplary embodiments of the inventive concept.

Referring to FIG. 1, a data storage device 1000 includes a flash memory1100 and a memory controller 1200. The data storage device 1000 mayinclude a data storage medium based on a flash memory such as a memorycard, a USB memory, a SSD, etc.

Referring to FIG. 1, the flash memory 1100 includes a memory cell array1110 and control logic 1160. The memory cell array 1110 includes aplurality of memory blocks. Each memory block has a three-dimensionalstructure (or a vertical structure) being formed in a directionperpendicular to a substrate. The control logic 1160 can controlprogram, read and erase operations using a command CMD, an address ADDRand a control signal CTRL.

The memory controller 1200 controls erase, write and read operationswith respect to the flash memory 1100 in response to a request of ahost. The memory controller 1200 includes a host interface 1210, a flashinterface 1220, a control unit 1230, a RAM 1240 and an ECC circuit 1250.

The memory controller 1200 exchanges data with the host through the hostinterface 1210. The memory controller 1200 exchanges data with the flashmemory 1100 through the flash interface 1220. The host interface 1210can be connected to the host through a parallel advanced technologyattachment (PATA) bus, a serial ATA (SATA) bus, a SCSI, a USB, a PCIe,etc.

The control unit 1230 can control the overall operation (e.g., read,write, file system management, bad page management) of the flash memory1100. The control unit 1230 may include a central processing unit (CPU),a processor, a SRAM, a DMA controller, etc.

The RAM 1240 operates according to a control of the control unit 1230and may be used as a work memory, a buffer memory, and a cache memory.In the case that the RAM 1240 is used as a work memory, data beingprocessed by the control unit 1230 is temporarily stored in the RAM1240. In the case that the RAM 1240 is used as a buffer memory, the RAM1240 is used to buffer data to be transmitted from the host to the flashmemory 1100 or from the flash memory 1100 to the host. In the case thatthe RAM 1240 is used as a cache memory, the RAM 1240 makes the low speedflash memory 1100 operate at high speed.

The ECC circuit 1250 generates an error correction code (ECC) forcorrecting a fail bit or an error bit of data received from the flashmemory 1100. The ECC circuit 1250 performs an error correct encoding ofdata being provided to the flash memory 1100 to form data to which aparity bit is added. The parity bit may be stored in the flash memory1100.

The ECC circuit 1250 can perform an error correct decoding on dataoutput from the flash memory 1100. The ECC circuit 1250 can correct anerror using parity. The ECC circuit 1250 can correct an error using acoded modulation such as a low density parity check (LDPC) code, a BCHcode, a turbo code, a Reed-Solomon code, a convolution code, a recursivesystematic code, a trellis-coded modulation, and a block codedmodulation.

FIG. 2 is a block diagram illustrating an example of a flash memoryillustrated in FIG. 1.

Referring to FIG. 2, the flash memory 1100 includes a memory cell array1110, an address decoder 1120, a page buffer circuit 1130, a datainput/output circuit 1140, a voltage generator 1150, control logic 1160,a temperature sensing circuit 1170 and a common source line driver 1180.

The memory cell array 1110 includes a plurality of memory blocksBLK1˜BLKz. Each memory block may have a three-dimensional structure (ora vertical structure). In a memory block having a two-dimensionalstructure, memory cells are formed in a direction parallel to asubstrate. In a memory block having a three-dimensional structure,memory cells are formed in a direction perpendicular to a substrate.

The address decoder 1120 is connected to the memory cell array 1110through select lines (SSL, GSL) or word lines WLs. The address decoder1120 receives a word line voltage VWL from the voltage generator 1150and is controlled by the control logic 1160. The address decoder 1120selects a word line during a program or read operation. A program,verification or read voltage may be provided to the selected word line.

The page buffer circuit 1130 is connected to the memory cell array 1110through bit lines BLs. The page buffer circuit 1130 may be constitutedby a plurality of page buffers (not shown). One bit line is connected toone page buffer but two or more bit lines may be connected to one pagebuffer. The page buffer circuit 1130 can temporarily store data to beprogrammed in a selected page or data read from a selected page.

The data input/output circuit 1140 is internally connected to the pagebuffer circuit 1130 through a data line DL and is externally connectedto the memory controller 1200 (refer to FIG. 1) through an input/outputline. The data input/output circuit 140 receives program data from thememory controller 1200 during a program operation and provides read datato the memory controller 1200 during a read operation.

The voltage generator 1150 receives power PWR from the memory controller1200 and can generate a word line voltage V_(WL) needed to read or writedata. A word line voltage V_(WL) is provided to the address decoder1120. The voltage generator 1150 can generate a high voltage HV higherthan a power supply voltage Vcc. The high voltage HV can be used as aprogram voltage Vpgm or a pass voltage Vpass during a program operation,as a read voltage Vread during a read operation and as an erase voltageVerase during an erase operation.

The voltage generator 1150 includes a Vpgm generator 1151, a Vvfygenerator 1152 and a Vcsl generator 1153. The Vpgm generator 1151generates a program voltage Vpgm being provided to a select word lineduring a program operation. As a program loop proceeds, the programvoltage Vpgm may increase. The Vvfy generator 1152 generates averification voltage Vvfy to verify whether a program operation issucceeded or not after the program voltage Vpgm is provided to everyprogram loop. The verification voltage Vvfy is constituted by a coarsevoltage and a fine voltage having a different level from the coarsevoltage to be provided to a word line. The Vcsl generator 1153 generatesa select line voltage being provided to a string select line SSL or aground select line GSL. Although not illustrated in the drawing, thevoltage generator 1150 may further include a Vpass generator generatinga pass voltage Vpass being provided to select and unselect word lines ina program operation. The pass voltage Vpass is maintained constant eventhough a program loop proceeds.

According to exemplary embodiments of the inventive concept, to increaseboosting efficiency, the flash memory device 1100 can reduce powerconsumption by controlling a level of a voltage which is generated bythe Vcsl generator 1153 to be applied to a common source line at everyprogram loop.

The control logic 1160 can control program, read and erase operations ofthe flash memory 1100 by using a command CMD, an address ADDR and acontrol signal CTRL being provided from the memory controller 1200. Forexample, in a program operation, the control logic 1160 can control theaddress decoder 1120 so that a program voltage Vpgm is provided to aselect word line and can control the page buffer circuit 1130 and thedata input/output circuit 1140 so that program data is provided to aselect page.

The temperature sensing circuit 1170 senses a temperature of theperiphery and provides a compensation signal CMP compensating a level ofa voltage being applied to the memory cell array 1110 to the voltagegenerator 1150. During a program operation, power consumption can bereduced while increasing boosting efficiency by compensating a level ofa voltage being applied to a common source line. If a temperature of theperiphery decreases, since a threshold voltage of a transistorincreases, a negative compensation voltage may be applied to the commonsource line. If a temperature of the periphery increases, since athreshold voltage of a transistor decreases, a positive compensationvoltage may be applied to the common source line. However, since variousdifferent factors besides temperature may affect a threshold voltage ofthe transistor, an inverse case may occur.

The common source line driver 1180 is connected between the voltagegenerator 1150 and the memory cell array 1110 to transmit Vcsl voltagebeing generated by the Vcsl generator 1153 to the memory cell array1110. The common source line driver 1180 can ground the common sourceline. According to a nonvolatile memory device in accordance withexemplary embodiments of the inventive concept, the common source lineCSL is grounded by controlling the common source line driver 1180 in aninitial loop of a program (for example, the percentage of cells beinginhibited among all memory cells is low) and thereby a level of avoltage being applied to the common source line become 0V. As a result,unnecessary power consumption caused by applying a common source linevoltage of the same level in all the program loop areas can be reduced.

FIG. 3 is a perspective view illustrating an example of athree-dimensional structure of a memory block illustrated in FIG. 2.Referring to FIG. 3, a memory block BLK1 is formed in a directionperpendicular to a substrate SUB. An n+ doping region is formed in thesubstrate SUB.

A gate electrode layer and an insulating layer are alternately depositedon the substrate SUB. An information storage layer may be formed betweenthe gate electrode layer and the insulation layer.

The gate electrode layer and the insulation layer are verticallypatterned to form a pillar of a V character shape. The pillar penetratesthe gate electrode layer and the insulation layer to be connected to thesubstrate. The inside of the pillar is a filling dielectric pattern andmay be constituted by insulating material such as silicon oxide. Theoutside of the pillar is a vertical active pattern and may beconstituted by channel semiconductor.

The gate electrode layer of the memory block BLK1 can be connected to aground select line GSL, a plurality of word lines WL1˜WL8 and a stringselect line SSL. The pillar of the memory block BLK1 can be connected toa plurality of bit lines BL1˜BL3. In FIG. 3, one memory block has twoselect lines SSL and GSL, eight word lines WL1˜WL8 and three bit linesBL1˜BL3 but the inventive concept is not limited to this example.

FIG. 4 is a top plan view illustrating A and B cross sections of amemory block illustrated in FIG. 3. The A cross section is a crosssectional view of a plane corresponding to the eighth word line WL8 andthe B cross section is a cross sectional view of a plane correspondingto the fourth word line WL4.

In the A and B cross sections, a memory cell may be constituted by afiling dielectric pattern, a vertical active pattern, an informationstorage layer and a gate electrode layer sequentially from the inside ofthe pillar. The internal filing dielectric pattern of the pillar may beformed of silicon oxide or air gap. The vertical active pattern may beformed of a P type silicon layer and operates as a channel of a memorycell.

The information storage layer may be constituted by a tunnel insulationlayer, a charge storage layer and a blocking insulation layer. Thetunnel insulation layer can operate as an insulation layer in whichcharges move by a tunneling effect. The charge storage layer may beconstituted by an insulation layer trapping charges. The charge storagelayer may be formed of, for example, a nitride layer SiN or a metal(aluminum or hafnium) oxide layer. The blocking insulation layer canoperate as an insulation layer between the gate electrode layer and thecharge storage layer. The blocking insulation layer may be formed of asilicon oxide layer. The tunnel insulation layer, the charge storagelayer and the blocking insulation layer may be formed by an insulationlayer of an oxide-nitride-oxide (ONO) structure.

Referring back to FIG. 3, a three-dimensional flash memory is formed byetching several thin layers at a time to form a hole and forming asilicon channel layer inside the hole. At this time, a diameter of thehole formed through an etching process may become different depending onits depth and may generally become small as approaching the substrate.As illustrated in FIG. 4, a radius R of a filling dielectric patterncorresponding to the eighth word line WL8 is greater than a radius r ofa filling dielectric pattern corresponding to the fourth word line WL4.

That phenomenon is due to a difference of etching depth and may become afactor of a characteristic difference of a memory cell connected to thefourth and eighth word lines WL4 and WL8. As a diameter of the pillarbecomes great, an effective area of the gate electrode layer is reducedand thereby a resistance of the gate electrode layer becomes high.Capacitance being formed between layers increases. Thus, as a diameterof the pillar increases, coupling capacitance and resistance of a memorycell increase. A resistance R and capacitance C of the eighth word lineWL8 located at the upper most layer of the pillar become maximum values.

Memory cells formed at the same height may have a similar cellcharacteristic. For example, since memory cells connected to the fourthword line WL4 have the same pillar diameter, coupling capacitances andresistances of the memory cells may have similar values.

FIG. 5 is an equivalent circuit diagram of the memory block illustratedin FIG. 3. Referring to FIG. 5, cell strings CS11˜CS33 are connectedbetween bit lines BL1˜BL3 and a common source line CSL. Each cell string(e.g., CS11) includes a ground select transistor GST, a plurality ofmemory cells MC1˜MC8 and a string select transistor SST.

The string select transistor SST is connected to a string select lineSSL. The string select line SSL is divided into first through thirdstring select lines SSL1˜SSL3. The ground select transistor GST isconnected to a ground select line GSL. Ground select lines GSL of thecell strings CS11˜CS33 are connected to one another. The string selecttransistor SST is connected to the bit line BL and the ground selecttransistor GST is connected to the common source line CSL.

The memory cells MC1˜MC8 are connected to respective word lines WL1˜WL8.A group of memory cells connected to one word line and programmed at thesame time is called a page. The memory block BLK1 is constituted by aplurality of pages. A plurality of pages may be connected to one wordline. Referring to FIG. 5, a word line (e.g., WL4) located at the sameheight from the common source line CSL is connected to three pages incommon.

Each memory cell can store one bit data or at least two bits data. Amemory cell that one bit data can be stored in one memory cell is calleda single level cell (SLC) or a single bit cell. A memory cell that atleast two bits data can be stored in one memory cell is called a multilevel cell (MLC) or a multi bit cell. In the case of a 2 bit MLC, twopage data is stored in one physical page. Thus, six page data can bestored in a memory cell connected to the fourth word line WL4.

FIG. 6A is a drawing illustrating a voltage being applied to a word lineduring a program operation in accordance with exemplary embodiments ofthe inventive concept. FIG. 6B is a drawing illustrating a voltage beingapplied to a common source line during a program operation in accordancewith exemplary embodiments of the inventive concept. FIGS. 6A and 6Billustrate a program operation with respect to a single level cell(SLC).

Referring to FIG. 6A, a program loop can be performed at least one time(for example, loop 1 through loop 7) which includes a step of applying aprogram voltage Vpgm and a step of applying a verification voltage Vvfyto program memory cells connected to one selected word line. At thistime, the program voltage Vpgm and the verification voltage Vvfy can begenerated by the Vpgm generator 1151 (refer to FIG. 2) and the Vvfygenerator 1152 (refer to FIG. 2) of the voltage generator 1150 (refer toFIG. 2) respectively. As the loop is repeatedly performed, the programvoltage can be increased by a predetermined voltage increment (ΔV). Thisis called an incremental step pulse programming (ISPP) method. Averification operation being performed at every program loop (forexample, loop 1 through loop 7) may include a first verificationoperation and a second verification operation. For example, the firstverification operation may be a coarse verification operation and thesecond verification operation may be a fine verification operation.However, the verification operation is not limited thereto. Theverification operation may be performed only once at every loop.

According to exemplary embodiments of the inventive concept, all theprogram loops (for example, loop 1 through loop 7) can be divided into aplurality of periods (for example, first through third periods)including at least one program loop. To increase boosting efficiencywhen each program operates, unnecessary power consumption can be reducedby making a voltage level being applied to a common source linedifferent at every period. For example, at an initial loop (e.g., loop 1or a loop around the loop 1), since most of the memory cells connectedone word line will be programmed, the percentage of cells beinginhibited is low. That is, the percentage of bit lines of which voltagesare boosted to a power supply voltage (e.g., 8V) among bit linesconnected to memory cells is low. In this case, since the percentage ofbit lines being boosted is low, if a voltage of the common source lineis maintained at a specific level to increase boosting efficiency ateven that program loop, this may cause unnecessary power consumption.

Thus, among all the program periods for programming memory cellsconnected to one word line, at an initial period (for example, period 1or periods 1 and 2) in which the percentage of cells being inhibited islow, a voltage of the common source line is maintained at 0V. As aprogram loop proceeds, a level of a voltage being applied to the commonsource line increases and thereby unnecessary power consumption can beprevented. A reference point by which all the program loops are dividedinto a plurality of periods may be determined by a memory vendor in amemory production stage. For example, all the program loops may bedivided so that program loops that the percentage of memory cells beinginhibited is lower than 10% may belong to the period 1, program loopsthat the percentage of memory cells being inhibited is higher than 10%and lower than 80% may belong to the period 2 and program loops that thepercentage of memory cells being inhibited is higher than 80% may belongto the period 3. The percentage of memory cells being inhibited which isa reference point of division is not limited to this example. The numberof periods being divided is also not limited to this example.

Referring to FIG. 6B, FIG. 6B illustrates a voltage level being appliedto the common source line while programming memory cells connected toone word line. Assume that seven loops are performed to program one wordline and the seven loops are divided into three periods. As describedabove, the number of periods is determined according to the percentageof memory cells being inhibited among all the memory cells. Thepercentage of memory cells that defines a boundary between periods maybe arbitrarily determined by a memory vendor in a memory productionstage. It may also be determined by firmware in a end user stage. Avoltage being applied to the common source line can be applied from wheneach loop begins until a supply of a program voltage Vpgm is cut off.After that, in a section in which a verification voltage Vvfy isapplied, a voltage being applied to the common source line may be 0V.

The period 1 means a section that the percentage of memory cells beinginhibited is low. This means that there is less need to boost bit linesconnected to unselect memory cells. For example, if the percentage ofmemory cells being inhibited among all the memory cells is lower than10%, loops (for example, loop 1 and loop 2) corresponding to that casemay be included in the period 1. Program errors that may occur because aboosting does not properly operate by keeping a voltage level of thecommon source line 0V can be corrected by the separate error correctioncircuit 1250 (refer to FIG. 1). That is, there is a trade-off between avoltage level control of the common source line and an error occurrence.

The period 2 means a section that there is increasingly need to boostbit lines connected to program inhibit memory cells because thepercentage of memory cells being inhibited becomes high while a programoperation is continuously performed. For example, if the percentage ofmemory cells being inhibited among all the memory cells is higher than10% and lower than 80%, loops (for example, loop 3, loop 4 and loop 5)corresponding to that case may be included in the period 2.

The period 3 means a section that the percentage of memory cells beinginhibited is high because a program operation is performed on most ofthe memory cells connected to one word line. That is, the period 3 meansa section that most of the memory cells are programmed and thereby thereis more increasingly need to boost bit lines connected to memory cellsto be program inhibited. For example, if the percentage of memory cellsbeing inhibited among all the memory cells is higher than 80%, loops(for example, loop 6 and loop 7) corresponding to that case may beincluded in the period 3. In the period 3, a voltage level being to thecommon source line may be 1.0V˜1.5V but the inventive concept is notlimited to this example.

As described above, when a program operation is performed on one wordline, according to the percentage of memory cells being inhibited,unnecessary power consumption can be prevented by controlling a level ofa voltage being to the common source line.

FIG. 7A is a drawing illustrating a voltage being applied to a word linewhen a program operation is performed on a multi level cell inaccordance with exemplary embodiments of the inventive concept. FIG. 7Bis a drawing illustrating a voltage being applied to a common sourceline in a program operation in accordance with exemplary embodiments ofthe inventive concept.

Referring to FIGS. 7A and 7B, an arbitrary loop n is illustrated among aplurality of loops needed to program memory cells connected to one wordline. As described in FIG. 6A, program voltages Vpgm being applied to aword line at every program loop may increase by a predetermined voltageincrement (e.g., ΔV) according to an ISPP method. A voltage beingapplied to the common source line can be applied from the time t0 wheneach loop begins until the time t2 when a supply of the program voltageVpgm is cut off. After that, in a section after the time t3 when averification voltage Vvfy begins to be applied, a voltage being appliedto the common source line may be 0V. While a program operation isperformed on a multi level cell MLC, since a method of reducing powerconsumption by controlling a voltage level being applied to the commonsource line is similar to that of a single level cell SLC, the detaileddescription is omitted.

FIGS. 8A, 8B and 8C are drawings illustrating examples of a voltagelevel applied to a common source line in one loop when a programoperation is performed. A section of t0˜t1 is a set up section, asection of t1˜t2 is a section of applying a program voltage to memorycells connected to a word line and a section of t2˜t3 is a standbysection to execute a program verification step.

At time t0, a program verification step of a previous loop is finishedand a new program loop begins. The section of t0˜t1 is a setup sectionand a voltage being applied to the common source line is graduallyincreased to minimize an effect that may exert on a memory cell in thesection of t0˜t1. Although a level of a voltage being applied to thecommon source line is gradually increased, the voltage level mayincrease in the form of an inverse exponential function as illustratedin the drawing by a parasitic capacitance being formed between thecommon source line and a bit line, between the common source line and aword line or between the common source line and a channel. This meansthat a current is needed to precharge a parasitic capacitance. Thesection of t1˜t2 is a section that a program voltage Vpgm is applied toa word line and at this time, a voltage of the common source linereaches a target level. Since a verification voltage Vvfy for judgingwhether a program is succeeded or not is applied to a word line fromtime t3, the voltage of the common source line has to be completelygrounded in the section of t2˜t3.

A threshold voltage of a transistor constituting a semiconductor deviceis changed by a peripheral temperature, it is necessary to compensatethe threshold voltage. Generally, if a peripheral temperature increases,a threshold voltage of a transistor is reduced. Thus, it is necessary toincrease a level of a voltage being applied to the common source line.If a peripheral temperature decreases, a threshold voltage of atransistor is lowered. Thus, it is necessary to lower a level of avoltage being applied to the common source line. The temperature sensingcircuit 1170 (refer to FIG. 2) senses a peripheral temperature totransmit a compensation signal CMP (refer to FIG. 2) controlling so thata level of a voltage being applied to the common source line iscompensated to the voltage generator 1150 (refer to FIG. 2). A voltageVcsl compensated by the compensation signal CMP can be supplied to thecommon source line of the memory cell array 1110 (refer to FIG. 2)through the common source line driver 1180 (refer to FIG. 1180).

Referring to FIG. 8B, a slope of the setup section (t0˜t1) can becontrolled by gradually increasing a voltage being applied to the commonsource line. In the case of a VNAND flash memory, since memory cells arevertically stacked on a substrate, it may be greatly affected by aparasitic capacitance compared with a general NAND flash memory. Asdescribed above, a parasitic capacitance may be formed between thecommon source line and a bit line, between the common source line and aword line or between the common source line and a channel. A parasiticcapacitance being formed between the common source line and a bit linemay affect a sensing operation and a recovery operation. A parasiticcapacitance being formed between the common source line and a word linemay affect program disturb. In the case that a voltage level of thecommon source line is rapidly increased, power noise may occur. Thus, toprevent that the parasitic capacitance is rapidly increased to affect amemory device, a slope of the setup section is controlled (e.g., {circlearound (a)} or {circle around (b)}) by controlling a speed that the Vcslgenerator 1153 (refer to FIG. 2) applies a voltage to the common sourceline.

Referring to FIG. 8C, immediately after a program voltage is applied ina section t1˜t2, a voltage being applied to the common source line canbe slowly reduced in a section t2˜t3. Although a power supply voltage iscut off in the section t2˜t3, because of an effect of a parasiticcapacitance, a voltage of the common source line is reduced in the formof an exponential function. Thus, to reduce an effect that may exert ona sensing operation, a recovery operation or a program disturb, a speedthat a voltage level of the common source line is reduced is controlled.For example, the control logic 1160 (refer to FIG. 2) can control timethat a level of the Vcsl is grounded (for example, {circle around (c)}or {circle around (d)}) by controlling the Vcsl generator 1153generating Vcsl being applied to the common source line through thecommon source line driver 1180.

FIG. 9 is a drawing illustrating a common source line driver inaccordance with exemplary embodiments of the inventive concept. Thecommon source line driver 1180 transmits Vcsl generated by the Vcslgenerator 1153 to the common source line or grounds the common sourceline. For example, the common source line driver 1180 may be constitutedby two transistors M1 and M2. As illustrated in the drawing, a drainelectrode of the M1 may be connected to the Vcsl generator 1153 and asource electrode of the M1 may be connected to a common source line. Adrain electrode of M2 may be connected to the source electrode of the M1and a source electrode of the M2 may be connected to a ground electrode.

For example, during a program operation, in the case that the percentageof memory cells being inhibited among all the memory cells is low andthereby there is less need to increase boosting efficiency (the period 1of FIGS. 6A and 6B), the M1 is turned off and the M2 is turned on andthereby the common source line can be grounded. In the case that as aprogram loop is repeated, the percentage of memory cells being inhibitedbecomes high and thereby there is increasingly need to increase boostingefficiency (the periods 2 and 3), the M1 is turned on and the M2 isturned off and thereby the common source line is grounded. As the numberof times the program loop is executed increases, the percentage ofmemory cells being inhibited becomes high, there is increasingly need toincrease boosting efficiency in a program operation. Thus, as the numberof times the program loop is executed increases, a voltage level of thecommon source line may increase.

According to exemplary embodiments of the inventive concept, a voltagelevel of the common source line can be changed according to thepercentage of memory cells being inhibited among all the memory cellswhile increasing a voltage level of the common source line in stagesfrom 0V to increase boosting efficiency in a program operation. That is,in the case of a program initial loop in which the percentage of memorycells being inhibited is low, a voltage level of the common source lineis lowered or grounded and in the case of a program loop in which thepercentage of memory cells being inhibited is high, a voltage level ofthe common source line is increased. By doing this, charge-dischargepower of the common source line that occupies 10˜15% of program powerconsumption of a VNAND flash memory device can be reduced by about 50%.

FIG. 10 is a block diagram illustrating an example that a data storagedevice in accordance with exemplary embodiments of the inventive conceptis applied to a memory card.

A memory card system 2000 includes a host 2100 and a memory card 2200.The host 2100 includes a host controller 2110 and a host connection unit2120. The memory card 2200 includes a card connection unit 2210, a cardcontroller 2220 and a flash memory 2230. The flash memory 2230 isembodied by the three-dimensional (3D) flash memory described above.

The host 2100 writes data in the memory card 2200 or reads data storedin the memory card 2200. The host controller 2110 transmits a command(e.g., a write command), a clock signal CLK generated from a clockgenerator in the host 3100 and data DATA to the memory card 2200 throughthe host connection unit 2120.

The card controller 2220 stores data in the flash memory 2230 insynchronization with a clock signal CLK generated from a clock generatorin the card controller 2220 in response to a write command receivedthrough the card connection unit 2210. The flash memory 2230 stores datatransmitted from the host 2100. In the case that the host 2100 is adigital camera, the flash memory stores image data.

FIG. 11 is a block diagram illustrating an example that a data storagedevice in accordance with exemplary embodiments of the inventive conceptis applied to a solid state drive SSD. Referring to FIG. 11, a SSDsystem 3000 includes a host 3100 and a SSD 3200.

The SSD 3200 exchanges a signal with the host 3100 through a signalconnector 3211 and receives power through a power connector 3221. TheSSD 3200 may include a plurality of flash memories 3201˜320 n, a SSDcontroller 3210 and an auxiliary power supply 3220.

The flash memories 3201˜320 n are used as a storage medium of the SSD3200. A nonvolatile memory device such as PRAM, a MRAM, a ReRAM, a FRAM,etc. besides the flash memory can be used as a storage medium of the SSD3200. The flash memories 3201˜320 n can be connected to the SSDcontroller 3210 through a plurality of channels CH1˜CHn. One or moreflash memories can be connected to each channel. Flash memoriesconnected to each channel can be connected to a same data bus.

The SSD controller 3210 exchanges a signal SGL with the host 3100through the signal connector 3211. The signal SGL includes a command, anaddress, data, etc. The SSD controller 3210 writes data in acorresponding flash memory or reads data from a corresponding flashmemory according to a command of the host 3100.

The auxiliary power supply 3220 is connected to the host 3100 throughthe power connector 3221. The auxiliary power supply 3220 can receivepower from the host 3100 to charge it. The auxiliary power supply 3220can be located inside or outside the SSD 3200. For example, theauxiliary power supply 3220 is located on a main board and can provideauxiliary power to the SSD 3200.

FIG. 12 is a block diagram illustrating a constitution of a SSDcontroller illustrated in FIG. 11. Referring to FIG. 12, the SSDcontroller 3210 includes a NVM interface 3211, a host interface 3212, anECC circuit 3213, a central processing unit (CPU) 3214 and a buffermemory 3215.

The NVM interface 3211 scatters data transmitted from the buffer memory3215 on respective channels CH1˜CHn. The NVM interface 3211 transmitsdata read from the flash memories 3201˜320 n to the buffer memory 3215.The NVM interface 3211 can use an interface method of a flash memory.That is, the SSD controller 3210 can perform a program, read or eraseoperation according to the interface method of the flash memory.

The host interface 3212 provides an interface with the SSD 3200 inresponse to a protocol of the host 3100. The host interface 3212 cancommunicate with the host 3100 using a universal serial bus (USB), asmall computer system interface (SCSI), a PCI express, an ATA, aparallel ATA (PATA), a serial ATA (SATA), a serial attached SCSI (SAS),etc. The host interface 3212 can perform a disk emulation function ofsupporting so that the host 3100 recognizes the SSD 3200 as a hard diskdrive (HDD).

The ECC circuit 3213 generates an error correction code ECC using databeing transmitted to the flash memories 3201˜320 n. The generated errorcorrection code ECC is stored in a spare area of the flash memories3201˜320 n. The ECC circuit 3213 detects an error of data read from theflash memories 3201˜320 n. if the detected error is correctable, the ECCcircuit 3123 corrects the detected error.

The central processing unit (CPU) 3214 analyzes and processes a signalSGL input from the host 3100. The central processing unit (CPU) 3214controls the host 3100 or the flash memories 3201˜320 n through the hostinterface 3212 or the NVM interface 3211. The central processing unit(CPU) 3214 controls an operation of the flash memories 3201˜320 naccording to firmware for driving the SSD 3200.

The buffer memory 3215 temporarily stores write data being provided fromthe host 3100 or data read from the flash memory. The buffer memory 3215can store metadata or cache data to be stored in the flash memories3201˜320 n. In a sudden power off operation, metadata or cache datastored in the buffer memory 3215 is stored in the flash memories3201˜320 n. The buffer memory 3215 may include a DRAM, a SRAM, etc.

FIG. 13 is a block diagram illustrating an example that a data storagedevice in accordance with exemplary embodiments of the inventive conceptis embodied by an electronic device. The electronic device 4000 can beembodied by a personal computer PC or a portable electronic device suchas a notebook computer, a cellular phone, a personal digital assistant(PDA) and a camera.

Referring to FIG. 13, the electronic device 4000 includes a memorysystem 4100, a power supply 4200, an auxiliary power supply 4250, acentral processing unit 4300, a RAM 4400, and a user interface 4500. Thememory system 4100 includes a flash memory 4110 and a memory controller4120.

According to exemplary embodiments of the inventive concept, in aprogram operation of a flash memory device, a level of a voltage beingapplied to a common source line to increase boosting efficiency can bedifferently controlled at every program period including at least oneprogram loop. Thus, in a program operation, power consumption can bereduced while boosting efficiency increases.

The above-disclosed subject matter is to be considered illustrative, andnot restrictive, and the appended claims are intended to cover all suchmodifications, enhancements, and other embodiments, which fall withinthe true spirit and scope of the inventive concept. Thus, to the maximumextent allowed by law, the scope of the inventive concept is to bedetermined by the broadest permissible interpretation of the followingclaims and their equivalents, and shall not be restricted or limited bythe foregoing detailed description.

What is claimed is:
 1. A method of programming a three-dimensional (3D)memory cell array which includes a plurality of memory cell strings,each of the memory cell strings extending in a direction vertical to asubstrate, an upper end of the memory cell string being connected with abit line and a lower end of the memory cell string being connected witha common source line (CSL), and each of the memory cell stringsincluding a plurality of memory cells, each of the plurality of memorycells being programmed by applying a programming voltage to a word lineconnected with the memory cell, the method comprising: executing a firstprogramming loop, the first programming loop comprising: applying afirst programming voltage to a selected word line; applying a firstcommon source line voltage to a common source line during applying thefirst programming voltage; applying a first verify voltage to theselected word line to determine whether the selected memory cells areprogram-passed or not; and applying a reference voltage to the commonsource line during applying the first verify voltage; and executing asecond programming loop, the second programming loop comprising:applying a second programming voltage to the selected word line;applying a second common source line voltage to the common source lineduring applying the second programming voltage; applying a second verifyvoltage to the selected word line to determine whether the selectedmemory cells are program-passed or not; and applying the referencevoltage to the common source line during applying the second verifyvoltage, wherein the second programming voltage is greater than thefirst programming voltage and the second common source line voltage isgreater than the first common source line voltage respectively.